1. Field of the Invention
The present invention relates to a pattern generation circuit, and more particularly, to a test pattern generation circuit and method for use with a self-diagnostic circuit (described hereinafter as a built-in self test circuit or xe2x80x9cBISTxe2x80x9d circuit) for generating a test pattern through use of a microinstruction code.
2. Background Art
FIG. 5 is a block diagram showing the configuration of a pattern generation circuit of a tester. In the drawing, RAM/ROM 1 is a first instruction code storage device for temporarily storing a microinstruction code and is constituted of RAM or ROM.
Reference symbol ADD 1 denotes an address signal to be supplied to the RAM/ROM 1; and CLK 1 denotes a clock signal. Reference symbol PG-1 denotes a pattern generation circuit which reads a microinstruction code INST.1 from the RAM/ROM 1 through use of the clock signal CLK 1 to thereby produce a test pattern DATA.1; RAM/ROM 2 denotes a second instruction code storage device which is identical in configuration and function with the RAM/ROM 1; ADD 2 denotes an address signal to be supplied to the RAM/ROM 2; and CLK 2 denotes a clock signal. Reference symbol PG-2 denotes a pattern generation circuit which reads a microinstruction code INST.2 from the RAM/ROM 2 through use of the clock signal CLK 2 to thereby produce a test pattern DATA. 2; and SEL denotes a selector which is connected to both the PG-1 and the PG-2 and selects either the test pattern DATA.1 or the test pattern DATA. 2.
FIG. 6 is a timing chart showing the correlation among the signals shown in FIG. 5. Referring to FIG. 6, reference symbols A0 through A3 denote address values of RAM/ROM, and Code.0 through Code.2 denote instruction codes for respective address values.
The circuit shown in FIG. 5 adopts a multi-bank interleaving method. According to the method, memory for temporarily storing a microinstruction code is divided into two banks; namely, the RAM/ROM 1 and the RAM/ROM 2. The memory for storing a continuous address signal ADD 1 and the memory for storing a continuous address signal ADD 2 are alternately assigned to the two banks. The circuit produces a test pattern a speed higher than a time required for accessing the RAM/ROM land the RAM/ROM 2. For these reasons, as shown in FIG. 6, a clock signal CLK 1 to be sent to the RAM/ROM 1 differs in phase from a clock signal CLK 2 to be sent to the RAM/ROM 2. Memory cycles A0, A2, . . . corresponded to the continuous address signal ADD 1 and memory cycles A1, A3, . . . corresponded to the continuous address signal ADD 2 are arranged so as to overlap each other.
When a microinstruction code stored in the RAM/ROM 1 is read through use of the clock signal CLK 1, a code 0 and a code 2 are output from the RAM/ROM 1 with a phase indicated by INST.1 in FIG. 6. Similarly, when a microinstruction code stored in the RAM/ROM 2 is read through use of the clock signal CLK 2, a code 1 and a code 3 are output from the RAM/ROM 2 with a phase indicated by INST.2. Two different codes INST.1 and INST.2 are output within a single clock cycle. The code INST.1 is input to the pattern generation circuit PG-1, and a corresponding test pattern signal DATA.1 is output from the pattern generation circuit PG-1. The code INST.2 is input to the pattern generation circuit PG-2, and a corresponding test pattern signal DATA.2 is output from the pattern generation circuit PG-2.
These test pattern signals DATA.1 and DATA.2 are input to the selector SEL. The test pattern signals are selected alternately, and the thus-selected test pattern signals are sequentially output. As a result, outputs denoted by OUT in FIG. 6 are produced.
The pattern generation circuit of the tester has the foregoing configuration. A plurality of blocks which are constituted of RAM/ROM and pattern generation circuits PG are required, thereby resulting in an increase in the area occupied by the circuit.
For this reason, the pattern generation circuit cannot be adopted as a pattern generation circuit of a BIST circuit, because limitations are imposed on the area occupied by the BIST circuit. Hence, the present invention is aimed at providing a test pattern generation circuit and method for use with a BIST circuit, which circuit and method provide the same function within a smaller area.
According to one aspect of the present invention, the present invention provides a test pattern generation circuit for use with a self-diagnostic circuit which produces a test pattern through use of a microinstruction code.
In one embodiment of the present invention, the circuit preferably comprises a memory device which temporarily stores the microinstruction code and outputs two different instruction codes within one clock cycle; a selector which receives output from the memory device and selectively delays the two instruction codes, thereby outputting one code; and a pattern generation circuit which produces a test pattern corresponding to output from the selector.
The selector can perform a selective delaying operation through use of a high-speed clock signal which is twice as fast as a clock signal to be sent to the memory device.
In another embodiment of the present invention the circuit comprises a memory device which temporarily stores the microinstruction code and outputs N different instruction codes within one clock cycle; a selector which receives output from the memory device and selectively delays N instruction codes through use of a clock signal which is N times as fast as a clock signal to be sent to the memory device, thereby outputting one code; and a pattern generation circuit which produces a test pattern corresponding to output from the selector.
According to another aspect of the present invention, the present invention provides a test pattern generation method for use with a self-diagnostic circuit which produces a test pattern through use of a microinstruction code.
In one embodiment, the method comprises outputting within one clock cycle two different instruction codes from a memory device which temporarily stores the microinstruction codes; selectively delaying the instruction codes by use of a selector, thereby producing one code; and producing a test pattern corresponding to output from the selector by use of a pattern generation circuit.
The selector can perform a selective delaying operation through use of a high-speed clock signal which is twice as fast as a clock signal to be sent to the memory device.
In another embodiment, the method comprises outputting within one clock cycle N different instruction codes from a memory device which temporarily stores the microinstruction codes; selectively delaying the instruction codes by use of a selector to which is imparted a clock signal N times as fast as a clock signal to be sent to the memory device, thereby producing one code; and producing a test pattern corresponding to output from the selector by use of a pattern generation circuit.
Other and further objects, features and advantages of the invention will appear more fully from the following description.